1. Field of the Invention
The present invention relates generally to data caches, and in particular to methods and mechanisms for reducing leakage current in data caches during periods of low activity.
2. Description of the Related Art
Modern day mobile electronic devices often include multiple components or agents sharing access to one or more memory devices. These multiple agents may make large numbers of requests to memory, and as the number of these requests increases, the power consumption of the device increases, which limits the battery life of the device. One approach for reducing power consumption is to try to reduce the number of times that off-chip memory is accessed by caching data in or near the processor.
Conventional caches are typically coupled to or nearby a processor and store data that is frequently accessed by the processor to reduce latency. In a conventional cache, periods of inactivity may occur when the cache (or a portion of the cache) is not accessed for a certain amount of time. If the cache is not being accessed but is still supplied with a voltage sufficient for allowing accesses, leakage current will be lost without any corresponding benefit to the processor. Additionally, as the temperature of the processor increases, the amount of leakage current also increases.